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Lecturer(s)
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Poupa Martin, Doc. Ing. Ph.D.
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Burian Petr, Ing. Ph.D.
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Course content
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1. Introduction, history of programmable logic devices, realization logic functions by PLD, SPLD architecture 2. Architectures of CPLD and FPGA. Basics of VHDL language, syntax, entity, architecture, design stages 3. Concurrent statements - unconditional, conditional and select statements, components, processes 4. MUX (when-else, with-select, process-case), processes, sensitivity list, wait statement 5. Flip flops - RS, D, parametrizable code using generate and loop 6. Static Time Analysis, specification of properties and requirements for time constraints (SDC) 7. Realization of memories (asynchronous/ synchronous, ROM, single and dual port RAM, FIFO) 8. Automatized test benches, serial transmitter and receiver (USART) 9. Architectures and features of modern FPGA devices 10. Attributes of types, subtypes, arrays, signals and entities, user defined attributes 11. Libraries and packages, Library of Paremeterizable Modules (LPM 2 0 0), work with files 12. Finite state automatons (Moore and Mealy type) in VHDL, standard VHDL 2008 13. Principles of digital circuit design, data exchange between different time domains 14. Realization and usage of software processors in FPGA devices
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Learning activities and teaching methods
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Lecture with practical applications, Students' portfolio, One-to-One tutorial, Task-based study method, Individual study, Self-study of literature
- Preparation for formative assessments (2-20)
- 2 hours per semester
- Presentation preparation (report) (1-10)
- 2 hours per semester
- Contact hours
- 26 hours per semester
- Practical training (number of hours)
- 26 hours per semester
- Preparation for an examination (30-60)
- 30 hours per semester
- Individual project (40)
- 20 hours per semester
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| prerequisite |
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| Knowledge |
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| describe logic gates decoders, multiplexers, priority coders |
| describe circuits for basic arithmetic operations |
| describe flip-flops, counters, registers, digital phase-locked loops |
| describe Memories - RAM, ROM, static, dynamic, SDRAM, special memory types - LIFO, FIFO, dual-port |
| describe finite state automatons |
| describe pipe-lining, synchronization |
| describe hazards and principles of their elimination |
| Skills |
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| understand the function of a digital circuit |
| design basic digital circuits |
| analyze complex digital systems |
| algorithmize |
| code formatting |
| Competences |
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| N/A |
| N/A |
| learning outcomes |
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| Knowledge |
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| describe CPLD and FPGA device architectures |
| describe syntax of VHDL language |
| Skills |
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| use the VHDL language for description, simulation and synthesis of digital circuits |
| use a VHDL simulator |
| use development system for the synthesis of circuits into the FPGA and CPLD |
| design several examples and verify them by the simulation and by a practical implementation in the FPGA device |
| teaching methods |
|---|
| Knowledge |
|---|
| Lecture |
| Laboratory work |
| Task-based study method |
| Interactive lecture |
| Individual study |
| Students' portfolio |
| Self-study of literature |
| Skills |
|---|
| Lecture |
| Practicum |
| Task-based study method |
| Interactive lecture |
| Individual study |
| Self-study of literature |
| Students' portfolio |
| assessment methods |
|---|
| Knowledge |
|---|
| Written exam |
| Oral exam |
| Seminar work |
| Skills |
|---|
| Seminar work |
| Skills demonstration during practicum |
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Recommended literature
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Ashenden, Peter J.; Lewis, Jim. VHDL-2008 : just the new stuff. Amsterdam : Elsevier/Morgan Kaufmann, 2008. ISBN 978-0-12-374249-0.
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Ashenden, Peter J. The designer's guide to VHDL. Third edition. 2008. ISBN 978-0-12-088785-9.
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Pinker, Jiří; Poupa, Martin. Číslicové systémy a jazyk VHDL. Praha : BEN - technická literatura, 2006. ISBN 80-7300-198-5.
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Rushton, Andrew. VHDL for logic synthesis. 2nd ed. Chichester : John Wiley & Sons, 2000. ISBN 0-471-98325-X.
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Skahill, Kevin. VHDL for programmable logic. Reading : Addison-Wesley, 1996. ISBN 0-201-89573-0.
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Šťastný, Jakub. FPGA prakticky : realizace číslicových systémů pro programovatelná hradlová pole. 1. vyd. Praha : BEN - technická literatura, 2010. ISBN 978-80-7300-261-9.
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