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KEI/PLO
Programmable Logic Devices
Guarantors: Doc. Ing. Martin Poupa, Ph.D.
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Course annotation
KEI/PLO
-IS/STAG
| The course explains the basics of CPLD and FPGA architectures of different manufacturers, function and application of programmable logic devices and basics of VHDL language. Next course explains description of the digital system by VHDL language (a description of the logic gates, multiplexers, flip-flops, RAM, ROM, state machines, RTL description, the synchronous design). Design and verification of functions of the proposed digital system in VHDL by functional and timing simulation, the practical verification of the design in the FPGA device. |
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Overview of lecture topics
| 1. |
Introduction, prog. log. circuits, development generations of PLD circuits, implementation of logos. functions in PLD. |
| 2. |
SPLD, CPLD and FPGA architectures. Basics of VHDL language, syntax, entity, architecture.
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Parallel statements - unconditional, conditional and selective expressions, components, processes.
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MUX (when-else, with-select, process-case), processes, sensitivity list, wait. |
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Description of flip-flops RS, D, parameterizable code using generate, loop. |
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Architectures and properties of modern FPGA circuits. |
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Memory implementation (asynchronous / synchronous ROM, one and two gateway RAM, FIFO). |
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Architectures and properties of modern CPLD circuits. |
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Automated test benche, serial transmitter and receiver. |
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Attributes of types, subtypes, fields, signals and entities, user-defined attributes. |
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Package libraries, library of parameterizable modules. |
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Description of Moore and Mealy state machines in VHDL, work with files. |
| 13. |
Implementation and use of software processors. |
| 14. |
Digital signal processing in FPGA circuits. |
Last updated:
26.06.2021
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