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Main menu for Browse IS/STAG
Course info
KEI / PLO
:
Course description
Department/Unit / Abbreviation
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KEI
/
PLO
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Academic Year
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2023/2024
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Academic Year
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2023/2024
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Title
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Programmable Logic Devices
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Form of course completion
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Exam
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Form of course completion
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Exam
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Accredited / Credits
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Yes,
4
Cred.
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Type of completion
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Combined
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Type of completion
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Combined
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Time requirements
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Lecture
2
[Hours/Week]
Tutorial
2
[Hours/Week]
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Course credit prior to examination
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Yes
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Course credit prior to examination
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Yes
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Automatic acceptance of credit before examination
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Yes in the case of a previous evaluation 4 nebo nic.
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Included in study average
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YES
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Language of instruction
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Czech, English
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Occ/max
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Automatic acceptance of credit before examination
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Yes in the case of a previous evaluation 4 nebo nic.
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Summer semester
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0 / -
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0 / -
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0 / -
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Included in study average
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YES
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Winter semester
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26 / -
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0 / -
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0 / -
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Repeated registration
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NO
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Repeated registration
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NO
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Timetable
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Yes
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Semester taught
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Winter semester
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Semester taught
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Winter semester
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Minimum (B + C) students
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10
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Optional course |
Yes
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Optional course
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Yes
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Language of instruction
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Czech, English
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Internship duration
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0
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No. of hours of on-premise lessons |
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Evaluation scale |
1|2|3|4 |
Periodicity |
každý rok
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Evaluation scale for credit before examination |
S|N |
Periodicita upřesnění |
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Fundamental theoretical course |
No
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Fundamental course |
Yes
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Fundamental theoretical course |
No
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Evaluation scale |
1|2|3|4 |
Evaluation scale for credit before examination |
S|N |
Substituted course
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KAE/PLO
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Preclusive courses
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N/A
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Prerequisite courses
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N/A
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Informally recommended courses
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N/A
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Courses depending on this Course
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KEI/SNEAP
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Histogram of students' grades over the years:
Graphic PNG
,
XLS
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Course objectives:
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The course explains the basics of CPLD and FPGA architectures of different manufacturers, function and application of programmable logic devices and basics of VHDL language. Next course explains description of the digital system by VHDL language (a description of the logic gates, multiplexers, flip-flops, RAM, ROM, state machines, RTL description, the synchronous design). Design and verification of functions of the proposed digital system in VHDL by functional and timing simulation, the practical verification of the design in the FPGA device.
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Requirements on student
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Requirements for examination:
Credit: completion of laboratory exercises, a presentation of independent work.
Exam: knowledge of the lectures and exercises, the ability to apply knowledge.
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Content
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1. Introduction, history of programmable logic devices, realization logic functions by PLD, SPLD architecture
2. Architectures of CPLD and FPGA. Basics of VHDL language, syntax, entity, architecture, design stages
3. Concurrent statements - unconditional, conditional and select statements, components, processes
4. MUX (when-else, with-select, process-case), processes, sensitivity list, wait statement
5. Flip flops - RS, D, parametrizable code using generate and loop
6. Static Time Analysis, specification of properties and requirements for time constraints (SDC)
7. Realization of memories (asynchronous/ synchronous, ROM, single and dual port RAM, FIFO)
8. Automatized test benches, serial transmitter and receiver (USART)
9. Architectures and features of modern FPGA devices
10. Attributes of types, subtypes, arrays, signals and entities, user defined attributes
11. Libraries and packages, Library of Paremeterizable Modules (LPM 2 0 0), work with files
12. Finite state automatons (Moore and Mealy type) in VHDL, standard VHDL 2008
13. Principles of digital circuit design, data exchange between different time domains
14. Realization and usage of software processors in FPGA devices
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Activities
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Fields of study
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Guarantors and lecturers
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Literature
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-
Basic:
Pinker, Jiří; Poupa, Martin. Číslicové systémy a jazyk VHDL. Praha : BEN - technická literatura, 2006. ISBN 80-7300-198-5.
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Extending:
Slidy přednášek předmětu PLO
(Poupa Martin)
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Recommended:
Šťastný, Jakub. FPGA prakticky : realizace číslicových systémů pro programovatelná hradlová pole. 1. vyd. Praha : BEN - technická literatura, 2010. ISBN 978-80-7300-261-9.
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Recommended:
Ashenden, Peter J. The designer's guide to VHDL. Third edition. 2008. ISBN 978-0-12-088785-9.
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Recommended:
Rushton, Andrew. VHDL for logic synthesis. 2nd ed. Chichester : John Wiley & Sons, 2000. ISBN 0-471-98325-X.
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Recommended:
Skahill, Kevin. VHDL for programmable logic. Reading : Addison-Wesley, 1996. ISBN 0-201-89573-0.
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Recommended:
Ashenden, Peter J.; Lewis, Jim. VHDL-2008 : just the new stuff. Amsterdam : Elsevier/Morgan Kaufmann, 2008. ISBN 978-0-12-374249-0.
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On-line library catalogues
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Time requirements
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All forms of study
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Activities
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Time requirements for activity [h]
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Preparation for formative assessments (2-20)
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2
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Presentation preparation (report) (1-10)
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2
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Individual project (40)
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20
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Practical training (number of hours)
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26
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Preparation for an examination (30-60)
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30
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Contact hours
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26
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Total
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106
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Prerequisites
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Knowledge - students are expected to possess the following knowledge before the course commences to finish it successfully: |
describe logic gates decoders, multiplexers, priority coders |
describe circuits for basic arithmetic operations |
describe flip-flops, counters, registers, digital phase-locked loops |
describe Memories - RAM, ROM, static, dynamic, SDRAM, special memory types - LIFO, FIFO, dual-port |
describe finite state automatons |
describe pipe-lining, synchronization |
describe hazards and principles of their elimination |
Skills - students are expected to possess the following skills before the course commences to finish it successfully: |
understand the function of a digital circuit |
design basic digital circuits |
analyze complex digital systems |
algorithmize |
code formatting |
Competences - students are expected to possess the following competences before the course commences to finish it successfully: |
N/A |
N/A |
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Learning outcomes
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Knowledge - knowledge resulting from the course: |
describe CPLD and FPGA device architectures |
describe syntax of VHDL language |
Skills - skills resulting from the course: |
use the VHDL language for description, simulation and synthesis of digital circuits |
use a VHDL simulator |
use development system for the synthesis of circuits into the FPGA and CPLD |
design several examples and verify them by the simulation and by a practical implementation in the FPGA device |
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Assessment methods
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Knowledge - knowledge achieved by taking this course are verified by the following means: |
Written exam |
Oral exam |
Seminar work |
Skills - skills achieved by taking this course are verified by the following means: |
Seminar work |
Skills demonstration during practicum |
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Teaching methods
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Knowledge - the following training methods are used to achieve the required knowledge: |
Lecture |
Laboratory work |
Task-based study method |
Interactive lecture |
Individual study |
Students' portfolio |
Self-study of literature |
Skills - the following training methods are used to achieve the required skills: |
Lecture |
Practicum |
Task-based study method |
Interactive lecture |
Individual study |
Self-study of literature |
Students' portfolio |
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